m.188betcom�ֻ��- 知识产权 (IP) 保护和FPGA设计安全性- 爱特公司厂商_在线座谈

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座谈主题：知识产权 (IP) 保护和FPGA设计安全性
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[问：zmeng]	FPGA可以编写多大规模的门电路？是否适合于混合电路？
[答：Albert_Tai]	Modern FPGA has already exceeded million gate.	[2003-5-22 10:39:44]
[问：zhenbo]	actel的APA系列FPGA的安全性是不是比其反熔丝的安全性差一些?
[答：Albert_Tai]	APA"s security is a little bit lower than antifuse, but is already high enough to block all security attacks.	[2003-5-22 10:40:57]
[问：lxy9712]	FPGA设计的安全性和CPLD设计的安全性是不是一致的？
[答：Albert_Tai]	CPLD normally is less complex than FPGA, and is based on macro cell architecture. It is MUCH easier to crack an CPLD than antifuse/flash based FPGA	[2003-5-22 10:42:02]
[问：xzzss]	我相对测量的电网电压的频率来做倍频，FPGA能否直接把模拟信号的输入变成是输入信号256倍频率的数字信号输出？CPLD管脚信号的输入是否一定要是数字信号，用它如何来实现256倍频率的输出？谢谢！
[答：Albert_Tai]	Actel APA (flash based) and Axcelerator (antifuse based) has internal analogy PLL, which allows frequency multiplication to be performed on the FPGA.You"re right, virtually all CPLD does not have analogy PLL and only allow digital signal input.	[2003-5-22 10:44:27]
[问：xzzss]	FPGA和CPLD在输入，输出信号上有什么差别吗？
[答：Albert_Tai]	There is no much different in terms of input/output signal between FPGA and CPLD.	[2003-5-22 10:45:11]
[问：jodanchen]	贵司的FPGA与其他公司的FPGA相比，具有哪些优点？
[答：Albert_Tai]	All of Actel"s FPGA are single chip, no need to use external EEPROM/MCU to perform power-up configuration. So the security is much higher than other SRAM based FPGA.And, antifuse/flash based FPGA are live at power-up, no need to wait the external EEPROM/MCU to configure it, and they all have low power consumption.	[2003-5-22 10:47:28]
[问：zhang jianlong710]	fpga设计安全的主要原理是什么？是否主要从硬件方面考虑么？可否软硬件结合？
[答：Albert_Tai]	The most important security aspect of FPGA design is device selection. If the protection at device is not sufficient, then it is meaningless to use higher level protection scheme, like software or watermark.	[2003-5-22 10:49:03]
[问：ly2002 _QG172]	1、ACTEL器件进行IP保护的原理是什麽？2、和同等规模的其它公司的器件相比在资源（RAM、逻辑单元、D触发器）和价格上的情况是什麽样的？3、我的设计大概在50万门左右的规模，其中用到了大量的RAM，我选什麽样的器件比较合适呢？
[答：Albert_Tai]	The IP protection on Actel FPGA is acheived by the nature of antifuse and flash programming element, these two elements are non-volitale.Actel"s product are competitive in price for the same level of logic capacity/RAM resourceAPA family should fit you needs	[2003-5-22 10:51:43]
[问：gavinlu]	在FPGA安全性问题上，是否考虑过将数字水印技术整合到开发工具中，利用这种方法对IP进行保护？（我最近一直在做这方面的研究工作即FPGA数字水印技术，但是有时感觉到水印方案中有太多的人工干预呀，因为我们研究者没法将自己的水印方法整合到开发平台中，这是一大遗憾呀）谢谢！
[答：Albert_Tai]	Watermark is not an active mean to protect an IP. It is only used to prove that the original design was done by the owner. It happen when your design has already been cloned. The physical level protection is much more important. If the hacker cannot clone your design, the watermark will be useless	[2003-5-22 10:55:17]
[问：yilans@as ian-micro.com]	用FPGA设计的专用电路，其网表是否可能被复制出来
[答：Albert_Tai]	There are security mechanisum to prevent the readback of netlist in antifuse and flash based FPGA.	[2003-5-22 10:56:33]
[问：rain164]	请问能否用FPGA制作数据通信加密芯片？
[答：Albert_Tai]	Yes, it can.	[2003-5-22 10:56:54]
[问：tibetlee]	我想问的不是很贴题，但我需要ACTEL FAE的帮助。我正在测试APA150是否符合即往设计（以前使用ALTERA1K30）的需求，但是我发现Synplify对APA的支持不好，fanout对性能的影响太大，强制设定最大扇出为6后，TIMER报告频率提高，但实际工作的结果很不稳定.我的问题就是解决综合工具与布局步线工具之间矛盾的行之有效的方法是什么？
[答：Albert_Tai]	You may use the regional constrain, timing constrain and spine networks in APA to acheive higher performance.	[2003-5-22 10:58:26]
[问：tjl]	在应用FPGA设计的专用芯片中的网表，是否比较容易地被复制出来。
[答：Albert_Tai]	Depends on which kind of FPGA. SRAM based FPGA"s content is extremely easy to be copied, while antifuse and flash based FPGAs are virtually impossible	[2003-5-22 10:59:34]
[问：xiaoge]	请问:在一般的设计中,最常见的嵌入式系统的攻击方式有哪些以及如何解决。
[答：Albert_Tai]	Cloning are the most common type of attack in embedded systems. You may use antifuse or flash based FPGA to keep sensitive logics/designs out attack.	[2003-5-22 11:01:52]
[问：pabo]	我使用a1280xlcq172-883B设计的逻辑电路，前后仿真都正确。而且使用同一个熔丝文件共烧写了6片，其中5个工作正常，另外一片在数据处理时会发生规律比较固定的错误，请问因该如何检查？是否要利用特殊的设备或者软件？
[答：Albert_Tai]	Please check the clock skew with Timer, these kind of problems are mostly due to clock skew, especially if the design contains many clock signals	[2003-5-22 11:03:23]
[问：avlicht]	据我所知，IP分为软Ip和硬IP，硬IP的保密性还可以，软IP就比较难办了，那我想问的是：你们是怎么解决软IP的保密性问题的？还有就是FPGA的保密性不如CPLD，那么FPGA的配置又是怎么实现保密的呢？谢谢！
[答：Albert_Tai]	No matter soft/hard IP can enjoy the same level of security in flash/antifuse based FPGA.In fact, only SRAM based FPGA"s security is lower than CPLD, ALL antifuse and flash based FPGA security is MUCH higher than CPLD and SRAM FPGA.To acheive the highest level of security, these two kind of FPGAs are suggested to be programmed in a secured location	[2003-5-22 11:06:29]
[问：telefeng 12@163.com]	您好，请问FPGA的主要应用领域有哪些，以及同DSP在应用上有什么优势和不足？谢谢！
[答：Albert_Tai]	FPGA is a general purpose reprogrammable logic device, and can be used in virtually any area. For DSP kind of applications, if the algorithm is fixed, then it can be hardwired into FPGA. But it is not as cost effective as using standard DSP, because it was optimized for this kind of applications.	[2003-5-22 11:08:55]
[问：zhdang]	戴先生：您好！clock skew的判断是根据两触发器之间的数据延时，和CLK延时来判断的吗？如果是是不是每两个触发器之间都要这么做？如果有两个触发器的时钟不是同一个时钟，应该怎么判断？
[答：Albert_Tai]	Clock skew is the largest delay of a clock signal between two registers. If two connected registers use different clocks, then this is not a synchronous design, which is difficult to analyse the timing and is sensitive to variation in operating condition (temperature and voltage variations)	[2003-5-22 11:11:03]
[问：zhdang]	clock skew有什么办法解决？一遇到这样的问题就束手无策了，谢谢
[答：Albert_Tai]	Use global clock network can solve clock skew problem. APA family"s global clock networks can be splitted to acheive maximum 88 high speed and low skew clock signal, which can deal with most of clock skew problem	[2003-5-22 11:12:24]
[问：leleg]	ACTEL的FPGA安全性和其它厂家相比，有什么特色吗？
[答：Albert_Tai]	Actel"s FPGA is well know if its security and reliability throughout the world. Other SRAM based FPGA has no way to compete with us.	[2003-5-22 11:13:29]
[问：bly]	1、请问FPGA有无带CPU内核的？2、请问最低功耗能达到多少，低功耗的芯片类型都有哪几种？
[答：Albert_Tai]	There are FPGAs that has built-in hardwired CPU. In fact, you can implement any CPU in FPGA with soft IP core.Power consumption depends on many factors, such as supply voltage, clock speed, logic utilization, etc.All Actel"s FPGA are low power in nature, our eX family"s consumption is as low as 100uA	[2003-5-22 11:16:09]
[问：yingyin969 @hotmail.com]	请问FPGa与现有的嵌入式系统相比有什么优势？
[答：Albert_Tai]	FPGA is good at handling high speed events and security protection (flash and antifuse FPGAs only).	[2003-5-22 11:17:23]
[问：赵昭旺]	Actel不需要PROM的FPGA那一款容量大、价格低？他的下载电缆价格？？
[答：Albert_Tai]	All Actel"s FPGA does not require external PROM. Our biggest antifuse device has 2 million gates, and our biggest flash device has one million gates. We have just released a low cost programmable for our APA family, for details you may contact our location distributors	[2003-5-22 11:19:32]
[问：eewwu @21cn.com]	ACTEL的反熔丝FPGA有没有ISP功能
[答：Albert_Tai]	Antifuse FPGA can not support ISP	[2003-5-22 11:20:02]
[问：ljp]	专家能否解释一下，用通用器件（DSP，MCU）、FPGA、ASIC实现相同功能任务时，三者在成本、性能等方面各自有何特长？
[答：Albert_Tai]	It is application dependents. DSP and MCU are good for jobs that require a lot of decision making. FPGAs are good at handling high speed hardware event and fixed data flow processing.	[2003-5-22 11:22:21]
[问：eewwu @21cn.com]	您所说的加密核是用来加密FPGA的编程数据还是用于一般的数据交换的保密加密应用？
[答：Albert_Tai]	The encryption/decryption IPs I mentioned are for data protection	[2003-5-22 11:23:30]
[问：ecnanji ng_EBY7E]	从SRAM FPGA 到Flash FPGA器件应用程序是否可以直接替换？
[答：Albert_Tai]	If the design on SRAM are in language format (VHDL/Verilog) then the conversion is pretty easy. Resynthesize the design is usually enough to do the conversion, sometime might involve a little bit changes in architectural specific macro, like embedded RAM. Generally speaking the process are very simple	[2003-5-22 11:25:31]
[问：qin]	如Actel AX2000 FPGA 有本53，000，000个反熔丝单元，128位加密后，FPGA的有用率大约是多少？
[答：Albert_Tai]	All FPGA in Axcelerator family can acheive 100% logic utilization, due to the full fracturable logic structure. At the same time, due to huge amount of antifuse, the design is guranteed to be 100% routable. The logic utiization of AES128 core varies between different vendors, you may go to our website for more details about these products.http://www.actel.com/products/ip/security.html	[2003-5-22 11:29:06]
[问：fyx123]	编译时选择的工业级芯片生成的BITSTREAM能烧到商业级芯片中吗？会出什么问题？反过来，会有什么问题？用FLASHPRO产生的EXIT11在BP的编程器中会出现吗？
[答：Albert_Tai]	It is not recommend to program bitstream design for different temp/speed grade in other devices. The timing characteristics of different speed/temp grade products are different. The most common problem in doing so is timing violation.If the cause of the EXIT11 is on the target board, then the same problem could happen.	[2003-5-22 11:32:42]
[问：赵昭旺]	ACtel的FPGA与Altera、Xinlinx的性能价格比较。在相同性能容量的产品中Actel的价格可否与他们相同？
[答：Albert_Tai]	We are competitive in price with Altera/Xilinx"s FPGAs	[2003-5-22 11:33:27]
[问：wuhan9719]	您在前面说,有第三方提供DES等加密核是吗?
[答：Albert_Tai]	Yes	[2003-5-22 11:33:39]
[问：hpf_972 @163.com]	我想问一下密钥是实时的还是固化的阿
[答：Albert_Tai]	Are you refering to the security key used in programming FlaslLock FPGA?	[2003-5-22 11:34:28]
[问：john603 @163.com]	一次性编程的ASIC和antifuse或FLASH的FPGA在保密性上有什么差别？
[答：Albert_Tai]	Antifuse based FPGA has the highest level of security, Flash based FPGA is the second best, and ASIC is the less secure one, although it is much better than SRAM FPGA	[2003-5-22 11:36:13]
[问：klbagio @163.com]	请问目前Actel公司的Flash FPGA内部时钟可以支持到多少MHz
[答：Albert_Tai]	The maximum internal speed of APA is 250MHz, and the hightest system performance is around 120MHz.	[2003-5-22 11:37:52]
[问：kittycharly @163.com]	CPLD在安全性上比FPGA要好，如何可以做到将FPGA的大容量与CPLD的高安全性相结合起来呢？
[答：Albert_Tai]	No, CPLD is secure than SRAM BASED FPGA, but not antifuse/flash based FPGAs.Actel"s antifuse and flash based security is MUCH higher than CPLD. We had customers who used CPLDs, and were cracked in two months after the product launch, after all they switch to our antifuse FPGAs, and that never happens again.	[2003-5-22 11:42:21]
[问：pabo]	为了适应空间的强辐射环境，在利用actel公司提供的fpga芯片进行逻辑设计时。主要应该注意那几项内容。对hdl语言描述的代码有什么特殊要求吗？有关抗辐射设计的参考资料在哪儿比较容易找到？
[答：Albert_Tai]	To deal with high radiation application, the internal registers are subjected to upset, triple voting registers may be used to replace ordinary flip-flop. The related application note can be found inhttp://www.actel.com/techdocs/appnotes/design_flow.asp	[2003-5-22 11:45:11]
[问：haoshuning]	Actel公司称，已推出低于$300的面向Proasic Plua系列的Starter Designer Kit（其中包括开发软件、编程器以及评估印制板）。国内厂商是否代理？
[答：Albert_Tai]	The starter kit is available now, please contact our distributors for pricing.	[2003-5-22 11:46:01]
[问：hpf_972 @163.com]	想问一下actel 加了密钥的芯片密钥是固化的吗还是每一次烧写时密钥不同
[答：Albert_Tai]	The security key used in encrypting the bitstream is fixed.	[2003-5-22 11:46:39]
[问：ljp]	为了安全保密Actel FPGA采用Silicon Sculptor及格Sculptor 软件，请问这过程是否可逆？
[答：Albert_Tai]	If the security feature on before programming, it is not reversable (cannot be readback).	[2003-5-22 11:47:35]
[问：pub@tech sino-telecom .com.cn]	您说CPLD的安全性比基于反熔丝的和flash的FPGA安全性差，更容易破解，请问CPLD加载原理和基于flash的FPGA加载原理相差很大吗？
[答：Albert_Tai]	It is not due to the programming methodology. CPLD"s logic density is much less than FPGA. FPGA"s secure programming element is MUCH more than CPLD, especially for antifuse, it is very very difficult to identify whether it has been programming or not as I mentioned in the presentation. To identify million of antifuse in a resonable time is virtually impossible.	[2003-5-22 11:50:13]
[问：hpf_972 @163.com]	想问一下公司的产品芯片在烧写时需要的配置方式有那些
[答：Albert_Tai]	Our antifuse FPGAs are programming with programmer called Silicon Sculptor.Our flash FPGAs can be programmed with Silicon Sculptor, Flash Pro, Flash Pro lite, or even ISP (MCU).	[2003-5-22 11:51:25]
[问：zmgong]	最近使用贵公司的FPGA，发现速率达不到38.88M，是否其布线资源有限
[答：Albert_Tai]	Which device are you using?	[2003-5-22 11:52:27]
[问：xzfang]	Flash Based的FPGA是否具有在线编程的能力？如果设计中采用了一个MCU,是否我可以设计一个程序用他对FPGA做编程？
[答：Albert_Tai]	Yes, you"re right!	[2003-5-22 11:52:59]
[问：pabo]	actel的fpga常应用在空间设计中，为了适应空间的强辐射环境，在设计是应注意什么？
[答：Albert_Tai]	The most important thing is to choose a radiation resistance part, like our RTSXS and RH family. Then you may use our triple voting flip-flop to increase the resistance to single event upset	[2003-5-22 11:54:18]
[问：MIchael _chur]	请问密钥是怎么存储在fpga中的？密钥的长度在多少位就可以满足加密要求了
[答：Albert_Tai]	The security key is store in the flash cell in the FPGA. The key length requirement is appliacation dependents. Event the shortest key (56-bit) takes years to crack. If the product"s life cycle (like POS device) is just a few years, then 56-bit is already good enough. Otherwise, you need to choose longer key length	[2003-5-22 11:56:30]
[问：xzfang]	Actel公司提供的标准加密IP在芯片上实现时其占用的资源是多少？其收费政策如何？
[答：Albert_Tai]	Please refer to the following URL for more details about the logic utilization of those IPshttp://www.actel.com/products/ip/security.htmlFor pricing, please contact our local distributors	[2003-5-22 11:57:33]
[问：ljp]	FPGA能代替ASIC，是指的那几方面？成本，集成度，芯片面积或设计复杂性？
[答：Albert_Tai]	Modern ASIC is competitive with medium scale ASIC in all aspects you have mentioned.	[2003-5-22 11:58:41]
[问：sunds99]	别人可能监视配置流，Config chip 和 FPGA chip 是分开的时候，有什么好的方法来加密？
[答：Albert_Tai]	That"s why you need antifuse or flash based FPGA, because they do not need external configuration device.	[2003-5-22 11:59:53]
[问：phdb]	如何评估器件的保密度？如何平衡保密度成本与保密性？其最优平衡点如何选择？
[答：Albert_Tai]	For a comparision of security offered by different technology, please refer to my presentation. The best solution is to use antifuse and flash fpga because they don"t add extra cost to the system, but will yield MUCH higher level of protection.	[2003-5-22 12:02:14]
[问：qin]	使用反熔丝FPGA时，当经加密程序已写入FPGA，发现程序出错，可否象FLASH一样可擦除重写？
[答：Albert_Tai]	Antifuse FPGA is one time programmble, so it cannot be erased. And, due to the exceptional high security level of antifuse FPGA, the bitstream does not need to be encyrpted.	[2003-5-22 12:03:20]
[问：ljp]	Antifuse FPGA的保密性能提高。是否成本上升？或者有用芯片面积减小？
[答：Albert_Tai]	No the sercurity of antifuse FPGA does comes with extra cost!	[2003-5-22 12:06:08]
[问：shijiangyi]	actel都支持那些软体？如何提高母片利用率？
[答：Albert_Tai]	Actel supports most popular thrid party EDA tools in the market. You may use our macro generator to product more area efficient and fast macro to increase the utilization	[2003-5-22 12:07:37]
[问：woshizh angliang]	请问AHDL语言现在和VHDL语言比功能上是否还有差距，以前是觉得AHDL好学一些，谢谢！
[答：Albert_Tai]	VHDL is MUCH MORE powerful than AHDL, if you have already managed AHDL, learning VHDL will be a easier task	[2003-5-22 12:08:48]

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