| 主题:基于DDS的RF频率合成器的应用考虑 |
| 在线问答 |
| [问：wangxin] |
DDS输出的频率经过缓冲器后，可否直接作为射频发射的主频，而不是去控制VCO？ |
| [答：LWS] |
surely you can if the frequency is you needed. |
[2003-9-4 10:41:13] |
| [问：zhai
shenghua] |
您好：请问，DDS器件AD9851BRS,在5V工作时，要求参考时钟输入为5V
CMOS电平，但市场上买到的晶振一般达不到这个输出幅度，我用电阻进行上拉，并在电阻和电源之间加入了一个磁珠进行隔离，输出幅度到到要求，这样是不是对DDS的工作产生了影响？导致输出频率不稳？怎么解决？ |
| [答：LWS] |
If you use the 5V to give the power supply to the oscillator. There
will be no problem. |
[2003-9-4 10:43:03] |
| [问：46836] |
我可否利用DDS直接作为本振输出几十到几百兆赫的频率源？ |
| [答：Mariah] |
Yes,DDS can be used as the frequency source. But you have to notice
the amplitude requirement of the clock input.Because the output of the DDS
is relatively low as the clock input. |
[2003-9-4 10:44:25] |
| [问：simmon] |
数模转换模数转换在现在在电子行业已经是不可缺的东西，我想问模拟信号转换的时候现在大都是转成精确的数字信号，不知道能否用模糊逻辑，让模拟信号进行模糊存储，现在数字信号转换的最高的精度是多少。谢谢！ |
| [答：LWS] |
The highest ADc resolution is 24 bit. And ADC/DAC is necessary for
almost all the system. |
[2003-9-4 10:46:05] |
| [问：deadlessbird] |
使用DDS作频率合成时 选择的采样频率
一般是输出频率几倍时效果最佳？ 比如输入10MHz 合成30MHz 一般选择输入几倍频较合适？ |
| [答：LWS] |
Normally, the input clock or the system clock should be 2 times faster
than the output. For 30MHz output, the system clock should be faster than
60MHz. Some parts may have multilier in the part. Ad9954 doe
example. |
[2003-9-4 10:47:49] |
| [问：gongjian88] |
请问当利用PLL倍频后，GHZ的频率的精度依然有那么高吗？ |
| [答：LWS] |
Yes, of course. |
[2003-9-4 10:48:57] |
| [问：KAIHONG] |
1.如何用AD9851,AD9852实现AM,FM音频调制及产生多波形信号,如三角波.2.如何减小DDS正弦波低频输出时失真较大的问题?3.在RF至1000MHz的信号源中,如何用DDS芯片实现高分辨率输出,如0.1HZ, 再者如何实现AM,FM音频调制?请一定赐教!不胜感激! |
| [答：Mariah] |
1.You can find the FM and AM modulation description in the
datasheet of AD9851 and AD9852.AD9851 and AD9852 have the ablity to output
triangle wave.2.You should pay attention to the filter design.
3.DDS can not output frequency up to 1000MHz. |
[2003-9-4 10:50:37] |
| [问：wenedi] |
adi公司专用的dds芯片中频率控制字是32位，rom中数据是16位的，最大的输出频率是多少呢？哪一款芯片？据我了解，adi公司的dds芯片内部采用pll进行倍频，这项技术的数据资料公开吗？ |
| [答：LWS] |
The highest output frequency is 500MHz. It is AD9858. the PLL
technology cannot be released yet. We are sorry for that. |
[2003-9-4 10:50:51] |
| [问：57692] |
由于DDS产生的频率范围比较大其后所跟的平滑滤波器的截止频率是否要跟随所产生的信号频率变化而变化？ |
| [答：LWS] |
The output filter should cover the frequency you wwanted to
get. |
[2003-9-4 10:52:08] |
| [问：56477] |
在ad9852和ad9854的评估板中，DDS的时钟都是采用差分双端的驱动方式（采用motorola公司的MC100LVEL16把单端时钟信号变成差分双端），直接采用单端时钟驱动方式会有什么不利之处吗？谢谢。 |
| [答：LWS] |
The performance will be degraded. You can find this from the
datasheet. |
[2003-9-4 10:53:02] |
| [问：cagwcagw] |
我们现在准备设计 45 到 75 Mhz
输出的频率合成器，请问能不能用ad9851直接设计，谐波问题怎样解决，是否要使用多个带通滤波器，能不能达到模拟锁相换的水平。谢谢！ |
| [答：Wayne] |
Yes, it"s easy to realize 45 - 75 MHz output using AD9851. Suggest to
use LPF instead of BPF, then it"ll be relatively easy to realize with a
single filter. For low frequency like your application, DDS can be better
choice compared to PLL because of its flexibility. |
[2003-9-4 10:53:10] |
| [问：ljp] |
相位/幅度的变换原理,请介绍一下?有无计算公式? |
| [答：LWS] |
You can download the DDS seminar from our website.The link is
http://www.analog.com/UploadedFiles/Tutorials/
54011189110016515183343533079104002517DDStutor.pdfOr
contact 800 810 1742, please. |
[2003-9-4 10:55:51] |
| [问：lq_lily] |
使用DDS芯片在做FSK调制的时候应注意什么问题，它是否能实现FSK信号的解调？ |
| [答：Mariah] |
DDS only can do FSK modulation. It can not do FSK demodulation. You
just need to configurate some register for FSK modulation. |
[2003-9-4 10:56:25] |
| [问：57692] |
据我所知，贵公司的AD9954存在静电防护不足的问题，请问该问题什么时候可望解决？何时可提供正常样品。早些时候据说要等到今年的秋天以后，现在时间方面有什么变化吗。谢谢。eewwu |
| [答：Pascal] |
AD9954 is not released yet, but will be released in late September, or
early October. There is an ESD issue with this part, it is a
pre-installation risk problem (for ESD damage, if it is exposed) but it is
not a performance issue. We will be correcting the problem and releasing
new silicon by January. |
[2003-9-4 10:56:40] |
| [问：72810] |
DDS产品目前的最高工作频率能达到多少？用于接力通信的电调频合有些什么样的技术难点？ 谢谢！ |
| [答：LWS] |
1GSPS, AD9858. But it is under export control now. For the details of
your project, please contact our 800 810 1742 |
[2003-9-4 10:56:43] |
| [问：qiangnet] |
DDS noise
rejection:能否介绍下DDS器件AD9850、AD9852等抗电源噪声的能力如何？（电源噪声多大的频率范围对输出抖动影响最大？）thanks
a lot! |
| [答：Pascal] |
We don"t specify PSRR - Power Supply Rejection Ratio. However, we
don"t see a problem, if the part is well bypassed at the power supply
pins. |
[2003-9-4 10:57:35] |
| [问：qin] |
就ADI公司的产品而言,DDS和PLL那个在市场上用得更多? |
| [答：LWS] |
ADI DDS and PLL is the best in the market. So all of them are popular
in China. |
[2003-9-4 10:57:50] |
| [问：95153] |
锁相环的鉴相频率分量在输出频谱中怎么消除？ |
| [答：LWS] |
Use the low-pass filter in the loop, you can cancel it. You can find
this from the textbook. |
[2003-9-4 10:58:48] |
| [问：lucifer_wyx] |
怎么在l频段实现分辨率为１Ｈz，捷变时间为１us，如１０００～１２００ＭＨz范围内频率合成？ |
| [答：LWS] |
You can consider the transation loop and the fractional PLL, ADF4252
for example. |
[2003-9-4 11:01:09] |
| [问：57692] |
您能再介绍一下AD9954的片上静态RAM的工作模式吗？在DDS
CORE时钟的控制下静态RAM的地址怎样变化？ |
| [答：Mariah] |
The RAM mode has a lot of functions. You can call toll-free number
800-810-1742 to get more information.The address of RAM can not be
changed by DDS CORE clock. |
[2003-9-4 11:01:53] |
| [问：racoon] |
以一个实例，谈用DDS如何实现跳频和解跳，还需要什么配套芯片。 |
| [答：LWS] |
Surely we have. Please download the article from the link
below:http://www.analog.com/UploadedFiles/Tutorials/
54011189110016515183343533079104002517DDStutor.pdfOr
call 800 810 1742 to get it. |
[2003-9-4 11:01:57] |
| [问：laiminfu] |
AD8302芯片，如果输入信号是多载波信号（或着CDMA信号），它能准确测量出它们的增益和相位吗？我在评估板上测量了一下，发现检测出来的增益和相位是周期信号，这样的话能否用来固定放大器的增益和相位？？ |
| [答：LWS] |
Surely, AD8302 can. For details, please contact 800 810 1742, becasue
I am not sure about your question now. |
[2003-9-4 11:03:18] |
| [问：LINZHIQI1] |
比 ad
9850/52/52/57 性能好的dds芯片有那些，如何能得到样片？ |
| [答：LWS] |
AD995X series and AD9858. AD9858 is under export control. For free
samples, please go to www.analog.com or contact our distributors. Or ask
for help from 800 810 1742 |
[2003-9-4 11:04:20] |
| [问：wenedi] |
1，对基于dds的射频信号进行调幅有哪些方式？2，如果用乘法器进行调幅，想输出15mhz的数字信号，一个周期内至少采样8点，又没有相应的乘法器完成调幅功能？3，如果采用双d/a方式在模拟部分调幅，对幅度控制字数字化的dac的各种参数与哪些因素有关？ |
| [答：Wayne] |
1. I think you"re talking about QDUC series like AD9857 which has
integrated Quadrature modulator. Then it can do 16QAM, 64QAM, 256QAM
depending on your applications.2. If you use multiplier for amplitude
modulator, as multipier is analog devices, which can"t output digital
signal. We"ve analog multiplier like AD834/835/539 which can meet your
request.3. I think you mean modulator instead of amplitude modulation
? Not sure about your question, please give a call to 800-810-1742 to give
details of your application, then we"ll have engineers to help
you. |
[2003-9-4 11:05:28] |
| [问：86222] |
能不能谈谈锁相环锁偏或锁不住频率的原因？如在FM频率调谐中，实际电路会出现在高频端（大于100MHz以上时）电台频率会锁不住或锁偏。谢谢！ |
| [答：LWS] |
The desing of loop filter is important. And with our PLL/DDS, using
our SW ADISimPLL, you can get a good design. For technical support, call
800 810 1742 |
[2003-9-4 11:05:51] |
| [问：melonpy] |
PLL和DLL的区别？ |
| [答：LWS] |
PLL is phase locked loop, DLL is delay locked loop. PLL is analog
technology and DLL is digital technology. |
[2003-9-4 11:06:45] |
| [问：hrgwang] |
我想利用ad9854实现宽带线性调频，计划采用步进fsk和内部自带的线性调频来实现，不知道哪种方案更好。如果我想利用两片ad9854合成正交两路的线性调频信号，可以吗？ |
| [答：Mariah] |
What do you mean the internal linear FM? AD9854 can implement ramped
FSK. You can generate two quadrature FM signal by using two pieces AD9854.
But you have to pay attention to synchronization of the two
parts. |
[2003-9-4 11:07:34] |
| [问：callus_luo] |
ad9854的输入时钟应该怎么设计 |
| [答：LWS] |
Please refer to the EVB schematic of AD9854. Normally, differetial
clock will be better than the single-ended clock. |
[2003-9-4 11:08:33] |
| [问：jjsen] |
请问：在100MHZ的输入时钟情况下，可以输出稳定的、周期均等的1M+10HZ或1M+20HZ吗? |
| [答：Mariah] |
Yes, the resolution of DDS is extremely high. So you can get the
output of 1M+10Hz and 1M+20Hz . |
[2003-9-4 11:08:58] |
| [问：19423] |
如果在DDS输出加单边带调制输出１GHz的信号，请问有合适的倍频器将信号倍频到９GHz吗？ |
| [答：LWS] |
We don"t have this kind of part now. And this kind of part is under
export control of USA government. |
[2003-9-4 11:09:58] |
| [问：kite] |
用DDS如何实现AM、FM、GFSK？ |
| [答：LWS] |
Please refer to the article from the
link:http://www.analog.com/UploadedFiles/Tutorials/
54011189110016515183343533079104002517DDStutor.pdfOr
call 800 810 1742 for support |
[2003-9-4 11:11:07] |
| [问：it00357] |
我用AD采样的数据进行频谱分析，通过DFT变换，再用DA转换输出到示波器，可是其波形并不理想，现成的频谱扫描仪由于速度太高也不能得到预想结果。请问有何器件或方法解决我的问题。谢谢！ |
| [答：Wayne] |
We"ve related ADC FIFO board for ADI ADCs, with software as ADC
Analyzer, which can help you realize ADC performance analyzing very
easily. |
[2003-9-4 11:11:35] |
| [问：yu_
hong_zhu] |
请问现在dds 芯片在m级性价比最高的是哪款？谢谢！ |
| [答：Mariah] |
Does m mean mega Hz? All of ADI DDS can output MHz signal.
You can consider AD983X series. |
[2003-9-4 11:11:46] |
| [问：kite] |
DDS如何与PLL结合用至更高频率？相噪如何测量？ |
| [答：LWS] |
Please refer to page 20-26 of the presentation. The phase noise is
measured by the spectrum anlyser. Any technical support needed, feel free
to contact 800 810 1742. |
[2003-9-4 11:12:21] |
| [问：68703] |
请问一下,DDS与PLL的混合使用,能不能产生高达几个GHz的正弦波 |
| [答：LWS] |
Yes, of course. Please refer to page 20 -26 of the
presentation. |
[2003-9-4 11:15:31] |
| [问：kgyip] |
基于DDS的RF频率合成器,频率锁定时间是多少？ |
| [答：Pascal] |
The frequency lock time is entirely determined by the PLL and loop
filter - that is the charge pump current, the size of the jump, the
reference frequency, and the loop filter characteristics. So, you can see
why we don"t spec this. It is dependent on the actual system
details. |
[2003-9-4 11:15:47] |
| [问：11509] |
您好，请问我用ad9853调制输出中频的qpsk信号在输出端是否需要再加上滤波器对信号整形滤波？也即其波形特性是否能满足一般性的通信要求！谢谢 |
| [答：LWS] |
Filter is necessaru for the output of AD9853. |
[2003-9-4 11:16:47] |
| [问：zxw] |
杂散是由什么造成的，自己用fpga实现dds的时候会不会有杂散，怎么预防？谢谢 |
| [答：Pascal] |
Yes. Even an FPGA implementation of a DDS has spurs. In fact, it is
worse than ADI DDS. Spurs come from the phase truncation, the angle to
amplitude conversion (or the accuracy of the values in the look-up table)
and the DAC characteristics. |
[2003-9-4 11:17:13] |
| [问：55224] |
请问ADF4360-1和-4什么时候发布 |
| [答：LWS] |
It is planned to release this September. |
[2003-9-4 11:17:22] |
| [问：shijh] |
DDS输出信号频率的最大能支持到多少？DDS对后置ADC有什么特殊要求？ |
| [答：Mariah] |
AD9858 can output up to 400MHz. But AD9858 is under the export control
of American government.DAC is integrated in DDS. The DAC in AD9858 is
10 bit. |
[2003-9-4 11:18:14] |
| [问：ssufn] |
请问如何得到更好的杂散性能？ |
| [答：Pascal] |
Use differential outputs - pay attention to balance in transformer.
Use separate analog and digital power supplies - well bypassed. Use a well
designed low pass reconstruction filter. |
[2003-9-4 11:18:41] |
| [问：cagwcagw] |
按刚才您的观点，使用下变频器的pll/dds组合，比使用除n分频的简单pll/dds组合性能要好，是这样吗？但是插入混频器会给环路滤波器带来一些额外的问题，这要考虑吗？ |
| [答：Wayne] |
When a DDS is combined with a PLL in a mixer upconversion scheme with
a PLL local oscillator (LO). The LO can be a fixed frequency PLL loop,
which can be highly optimized for stability and phase noise.This
architecture also results in a performance improvement with respect to
phase noise at RF, because the frequency gain is unity.Surely you need
to choose proper mixer, from the point of IP3 and noise
figure.... |
[2003-9-4 11:18:42] |
| [问：94981] |
我构想用AD9857，使用边带抑制的办法来实现SSB，不知道这样的方法，在实际实现中是否可行？ |
| [答：LWS] |
It is reasonable. |
[2003-9-4 11:19:47] |
| [问：86222] |
用AD9852能否直接实现AM和FM，如果能够，怎样实现？ |
| [答：LWS] |
AD9852 can be used as the FM. For AM you can control the input of
Rset. |
[2003-9-4 11:20:57] |
| [问：chaihonggui] |
通常如何控制DDS输出杂散？ |
| [答：Pascal] |
Use differential output - pay attention to good balance in
transformer. Use separate analog and digital power supplies - well
bypassed. Use well designed low pass reconstruction filter.Also,
frequency planning can select spur free zones. |
[2003-9-4 11:21:12] |
| [问：95153] |
ad的dds工作时的允许温度是多少，在使用中adi的dds的工作温度都很高，有没有什么好的方法来降低这个温度。 |
| [答：LWS] |
The operation temp is -40 t0 85 degree. The temp control can be
implemented by the good layout and using our new released parts
AD995X. |
[2003-9-4 11:22:34] |
| [问：18738] |
我的问题是，我想用AD9850和两个PLL来合成2Ghz左右的频率，输出高频处的VCO是否要求很高，有什么型号可以推荐？ |
| [答：Wayne] |
suggest you to use ADF4360. It"s a series of PLL with integrated VCO,
which can support up to 2.55GHz. |
[2003-9-4 11:22:42] |
| [问：84753] |
AD9852在FSK模式下两个频率调节字均可设置，在这种状态下可否输出两个不同的频率。 |
| [答：LWS] |
AD9852 has two ouputs. So you can ouput two different frequencies from
AD9852. |
[2003-9-4 11:24:20] |
| [问：hard22] |
我用的是ad9852,开始用的还可以,但后来设计电路时发现调节输出幅度的电阻必须加大,例如8k,如果还用3.9k的电阻,片子回很热,无法调试,请问一下这是为什么?谢谢! |
| [答：LWS] |
Please calculate the thermal. Refer to page 32 of the datasheet. And
your problem is strange, we ahve never meet such problem, maybe you should
use the AD9852ASQ. If you need technical support call 800 810
1742 |
[2003-9-4 11:27:54] |
| [问：zhai
shenghua] |
您好：DDS,AD9851工作时，温度为多少算是没有问题？我怎么总觉得它比较热？是板子上最热的器件，比电源管理还要热！！资料上说5V时功耗为500MW左右！ |
| [答：Wayne] |
You can find on the datasheet that the operation temperature for
AD9851 is -40 to 85 degree.It"s normal if it"s a little hot when it
works at fast clock. However, please make sure your schematics are
right. |
[2003-9-4 11:28:04] |
| [问：jjsen] |
请问：在DDS的输入时钟为100MHZ（认为是稳定的）的情况下，可以输出稳定的、每个周期都是均等的1M+10HZ或1M+10HZ吗？ |
| [答：LWS] |
The frequency resolution is very small for DDS. You can get your
output with the right part, AD9852, AD9952 for example. |
[2003-9-4 11:29:08] |
| [问：zhai
shenghua] |
您好：请问在用AD9851BRS产生的20MHz信号中，可以看到很明显的频率波纹抖动，这是什么原因？是不是镜像频率的干扰，通过70MHz低通滤波以后，有较为一定的改善！ |
| [答：LWS] |
I am sure this is the image. And the filter is necessary for the high
quality signal output. You can use spectrum analyser to find out its
frequency characteristics. Call 800 810 1742 for technical
support |
[2003-9-4 11:30:40] |
| [问：
ndshyw] |
用DDS做参考时,PLL倍频次数能做到多大?要保证输出范围内各频率点均要锁住.另外,如何尽可能减小杂散?可否做到-60dB以下?谢谢! |
| [答：LWS] |
PLL multiplier can be 20 in the most. And it is easy to get the -60dB
spur with the right filter in the output. |
[2003-9-4 11:32:30] |
| [问：zhshua] |
请问DDS器件AD9851所产生的40MHz信号频率不稳，总是有波动，怎么才能解决这个问题？ |
| [答：LWS] |
The performace should be in the frequency domain. And a filter
followed the houtput is necessary. With the right filter, the signal is
very beatiful. You can send mail to china.support@analog.com to get the
tested output. |
[2003-9-4 11:33:51] |
| [问：luckyjar] |
您好，我用ad9852，FSK模式做实验，产生10M左右信号，输出经51欧姆电阻转换为电压，幅度只有0.2伏左右。后面所接的晶体滤波器不能响应。能否增大电阻，以提高输出信号电平？ |
| [答：LWS] |
No. The output voltage for the AD9852 is -0.5V to 1.0V. For your
application, a high speed ADC is necessary. |
[2003-9-4 11:35:38] |
| [问：57692] |
如用AD9954的比较器产生方波在100MHz附近，
方波周期的抖动可否小于150ps？ |
| [答：Mariah] |
From AD9954 datasheet, the output jitter of the comparator is only
1ps. |
[2003-9-4 11:36:31] |
| [问：NAN
JINGLIU
CHANG] |
如何在实际的工程中，减小DDS输出的杂散信号？ |
| [答：LWS] |
Use the right filter after the DDS, and use the high quality
clock. |
[2003-9-4 11:37:10] |
| [问：61047] |
你好，能否介绍一下AD98XX系列的DA变换和幅度，相位调制功能 |
| [答：LWS] |
Please refer to the
articlehttp://www.analog.com/UploadedFiles/Tutorials/
54011189110016515183343533079104002517DDStutor.pdf |
[2003-9-4 11:37:43] |
| [问：liuchunyang] |
1、在使用DDS+PLL来产生RF信号时，怎样精确控制输出的相位，如果可以是否可以直接用这种方案来实现数字相位调制？那么调制带宽和环路带宽选择什么样的关系比较合适？如果用AD9854实现QPSK调制，调制速率能达到多少？2、DDS输出信号和参考时钟在相噪问题上是否也有一个可以估算的公式？ |
| [答：Pascal] |
1. When using a PLL loop driven by a DDS, there is no way to precisely
determine the phase - that is determined by the PLL loop. It will be a
function of the phase at the phase detector, which will be kept constant
by the loop.Modulation bandwidth must be less than the loop
bandwidth, or the loop will cancel it out, or not track the
modulation.The AD9854 can be QPSK modulated up to the SysClk rate,
but you would not want to do this. So, you should be able to use AD9854
for any reasonable QPSK rate.2. No. That has to be measuered on
the bench. It can also be predicted by design simulation, but there is no
"formula" that can give a meaningful value for phase noise. |
[2003-9-4 11:37:52] |
| [问：89279] |
刚才所介绍AD9858的频移环路，可以用在产生线性调频信号上吗？ |
| [答：LWS] |
Surely you can. |
[2003-9-4 11:38:20] |
| [问：57692] |
Is it possible to use the DDS AD9954 to
producea triangle wave by fill the on board 1024*32 SRAMwith data
someting like the anti sine functionof the address? |
| [答：Pascal] |
Yes. Set the tuning word to zero frequency. Use the RAM to drive the
phase offset word.Contact Ted Harris (ted.harris@analog.com) for
more details. |
[2003-9-4 11:38:58] |
| [问：11570] |
在ad9854中给出了Pipeline
Delays的指标，ad9858的内部时延指标可有？ |
| [答：Pascal] |
Pipeline delays indicate how many SysClock periods it takes for
certain changes to be apparent at the output of the DDS. It stems from the
fact that there is sequential logic (flip-flops) in the digital data chain
of the DDS. |
[2003-9-4 11:40:15] |
| [问：cagwcagw] |
刚才您讲到AD9856/7适用于任意波形合成，是这样吗，他们可以输出多高的频率，需要使用怎样的DSP配合？谢谢！ |
| [答：Wayne] |
AD9856/7 is not arbitray wave generator, they"ve 3 operating modes:
Quadrature Modulation Mode (Default), Single-Tone Mode, and Interpolating
DAC Mode.The REF clock input for AD9856/7 is 200MHz, basically it
requests that the system clock must be at least 2.5 times of output
frequency.DSP choosing will depends on your system data handling
ability requested. ADI has ADSP218x/219x as fixed point, ADSP2106x/2116x
(sharc series), Tigersharc series, and BF2153x (blackfin series). |
[2003-9-4 11:40:23] |
| [问：cagwcagw] |
按您刚才的讲解，使用插入混频器的pll/dds组合，性能要比使用除n的简单pll/dds组合，性能要好，是这样吗？但是插入混频器后所带来的对环路滤波器的影响如何考虑？ |
| [答：Pascal] |
The translation loop architecture (using a mixer) can give better
performance, especially phase noise, than direct driving of PLL. If the
PLL is used to provide the LO, then it is not usually changing frequency.
The loop filter should be designed for minimum phase noise. Bandwidth of
the PLL is not an issue, since the PLL doesn"t have to track frequency
changes. |
[2003-9-4 11:42:38] |
| [问：samire] |
如何降低DDS时钟发生器的抖动? |
| [答：LWS] |
Use the high quality input clock and the right filter after
it. |
[2003-9-4 11:42:39] |
| [问：jjsen] |
你们的产品中，精度最高的是那一系列芯片，精度有多高？ |
| [答：LWS] |
Which accuracy you referred to? For DAC, AD995X use the 14-bit
DAC. |
[2003-9-4 11:43:39] |
| [问：zhaishenghua] |
对DDS输出后端所加的滤波器有没有什么特殊要求？ |
| [答：LWS] |
Normally, we use epplitical filter after it. You can refer to the
filter in the EVB. |
[2003-9-4 11:45:01] |
| [问：94981] |
为用低频率输出的DDS来实现较高频率的合成，我希望对其输出的高次谐波进行代通选择，我希望知道通常这么做的话，一般取到几次谐波成分比较合理？ |
| [答：LWS] |
Please refer to the article
below:http://www.analog.com/UploadedFiles/Tutorials/
54011189110016515183343533079104002517DDStutor.pdfAny
technical support needed, call 800 810 1742, please. |
[2003-9-4 11:46:09] |
| [问：chizhipeng2] |
我们对AD9852内部全部寄存器写控制字后，对它进行读操作，为何有时只能读出控制寄存器４个字节，而其它起作用的寄存器却读不出来，但是它们确实起作用了 |
| [答：LWS] |
Some registers are readable, but some is write only. Please refer to
the datasheet of AD9852. |
[2003-9-4 11:46:54] |
| [问：84753] |
在用DDS与PLL组合用于镜像抑制时能否做到很宽的频率范围，例如从1MHz到1000MHz。用什么方法可以更好的抑制非谐波杂散，用高的DDS时钟取较低的使用频率是否有效。 天津德威 赵亚利 |
| [答：Pascal] |
One of the costs of using PLL in some DDS/PLL architectures is that
the bandwidth is limited to the range of the VCO.Spurious noise
needs to be controlled at all stages - at the output of the DDS, as well
in the PLL loop.Sometimes, using a high DDS clock and relatively
low output frequency can improve spur performance, but the reconstruction
filter cutoff needs to be set correspondingly low to filter out
harmonics. |
[2003-9-4 11:46:54] |
| [问：86222] |
我们想产生一个带宽1G的线性调频信号，载频为8G,想用AD9858产生100－200MHz的信号，调制到1G上，再通过倍频器多次倍频上去，我想请问这样会不会将杂散指标变得更坏？谢谢 |
| [答：Pascal] |
Yes. It will deteriorate. It is a mathematical necessity. The trick is
to allocate the SFDR budget well and control spurs and phase noise at each
stage as well as possible. |
[2003-9-4 11:48:10] |
| [问：19410] |
利用AD9858能否在进行相位调制的同时在子码内部再进行线性频率调制 |
| [答：LWS] |
AD9858 doesn"t have the ASK and PSK at the same time, you can consider
AD9954. |
[2003-9-4 11:48:17] |
| [问：57692] |
请问可否通过使AD9954的片上RAM的内容取与步长相对应的反正旋函数值从而实现三角波的输出？更进一步是否可以按照这个思路实现任意信号发生器？谢谢 |
| [答：Eagle] |
We have AD9856 and AD9857 which can realiza all kinds of wave form
modulate. AD9857 可以实现任意波形调制，包括三角波和SINC函数。 |
[2003-9-4 11:48:43] |
| [问：94981] |
我想问一下，用AD9857是否可以使用Hartley算法来实现SSB的波形生成，另外，可否则实现FM波形的合成 |
| [答：Pascal] |
Yes. The vectors for the I/Q input must be calculated by DSP or ASIC
before AD9857. If the waveform can be represented as a I/Q vector which is
within the bandwidth capability of the AD9857, then it can be
realized. |
[2003-9-4 11:49:52] |
| [问：lucifer_wyx] |
如何实现将DDS输出的较低频率的宽带信号搬移到GHz频段，要求切换时间较快，不采用闭环系统？ |
| [答：Eagle] |
建议使用AD9858，可以用带通滤波器直接取谐波，但幅度会较小。也可以用AD9858的混频器混到GHz。 |
[2003-9-4 11:50:26] |
| [问：刘伟] |
有DDS在WCDMA上应用的方案吗？ |
| [答：LWS] |
We has the use of AD9857 used in 3G. You should consider based on the
system design. |
[2003-9-4 11:50:50] |
| [问：ssufn] |
DDS+PLL用于跳频时，跳频速度尽量快的组合方法？ |
| [答：Eagle] |
用AD9858。400MHz以下直接用，GHz以上用混频器。 |
[2003-9-4 11:51:23] |
| [问：qin] |
我对PLL不太熟悉,请介绍其中的电荷泵的原理及作用.它和电源中的电荷泵有何区别? |
| [答：LWS] |
Please go to www.analog.com to download the Ask the Applications
Engineer—30/31. Or please refer to some textbooks. |
[2003-9-4 11:52:40] |
| [问：sum
mer_6018] |
DDS的相噪指标主要受什么因素的影响，在设计时需要注意哪些问题。 |
| [答：Eagle] |
主要是DDS时钟抖动和DDS通道字长和DAC的位数。布线时考虑时钟的屏蔽，防止干扰。 |
[2003-9-4 11:53:34] |
| [问：liu
chunyang] |
用DDS产生某频率点时，输出的信号的相位噪声和参考频率相噪是否也有一个可以估算的公式？ |
| [答：LWS] |
There is no equation to caculate the spurs. But we don know where is
the spur.Refer to the article
pleasehttp://www.analog.com/UploadedFiles/Tutorials/
54011189110016515183343533079104002517DDStutor.pdf |
[2003-9-4 11:54:22] |
| [问：yqiao225] |
有没有DVB-C调制器的解决方案？ |
| [答：Wayne] |
AD8345 is a 250-1000MHz Quadrature Modulator. If you are designing
QAM, we"ve Dual PLL like ADF4217/8, mixer like AD8343 for DC-2.5GHz, and
some cable drivers. |
[2003-9-4 11:54:35] |
| [问：68703] |
请问一下,DDS与PLL组合使用,能不能达到几个GHz的正弦波 |
| [答：LWS] |
Surely it can. Please refer to page 20-26 of the
presentation. |
[2003-9-4 11:54:45] |
| [问：samire] |
一般地说,
输出频率相同时,DDS和PLL那个成本会低些?频率稳定性会好些? |
| [答：Eagle] |
当然是PLL，有些PLL还会集成VCO，如ADF4360。但某些DDS如AD9833也很便宜。频率稳定性DDS为优。 |
[2003-9-4 11:55:13] |
| [问：DeFatta] |
能否用51单片机的串口来控制DDS？应注意什么？ |
| [答：LWS] |
Yes of course. You can send mail to china.support@analog.com to get
the codes. Or call 800 810 1742 to get technical support |
[2003-9-4 11:56:04] |
| [问：65577] |
1.目前DDS的输出频率能够到多少？制约因素是什么？2.DDS+PLL是不是还是增加了系统的响应时间，对于信道间隔小的系统不适合？ |
| [答：Pascal] |
The maximum output frequency of a DDS is about 40% of the clock
frequency. The AD9858 can clock at 1GHz, so its max frequency is about
400MHz. The fact that the DDS is limited to a little less than one-half of
the clock frequency is because it is producing a sampled analog signal,
which is subject to the Nyquist criteria.The operating speed of
our DDSs is largely determined by the state of the art in DAC
design.2) Yes, it does prolong the system response time, if the
PLL is in the direct signal chain (that is, not just an LO). The PLL loop
needs to be adequately designed for the desired response time or
bandwidth. |
[2003-9-4 11:57:43] |
| [问：jjsen] |
一般DDS的分辨率是多少？ |
| [答：LWS] |
This is decided by the resolution of the DDS and the master clock. For
example the resolution is 32-bit and the master clock is Fclk, then the
freqeucency resolution is Fclk/2exp(32). |
[2003-9-4 11:57:54] |
| [问：11509] |
请问dds
AD9853在输出调制信号后上变频射频输出时需要注意什么问题？对放大器和滤波器设计的主要要求是什么？谢谢 |
| [答：LWS] |
There is no special consideration. Pleas refer to the EVB
schematic. |
[2003-9-4 12:00:32] |
| [问：liu
chunyang] |
您好！请问用DDS+PLL方案怎样精确控制输出RF的相位？ |
| [答：Pascal] |
The output phase of a DDS+PLL is determined by the loop. The output
phase will be a function of the reference and the loop gain. |
[2003-9-4 12:00:33] |
| [问：guo.
hongtao] |
你们的ADF4252和ADF4153除了双环和单环区别外，两个的性能有多大区别。你们推荐哪个产品。 |
| [答：LWS] |
ADF4252 is dual loop, ADF4153 is single loop. There is no performace
difference. You have to select parts according to your system
requirement. |
[2003-9-4 12:01:50] |
| [问：qin] |
如何考虑或设计PLL中的回路滤波器?它的增益,带宽和衰减如何决定? |
| [答：Pascal] |
That depends on the system requirements. It must be determined on a
case-by-case basis. There is no one-size-fits-all answer to this
question.Please refer to SimPLL for some help with designing PLL
loop filters. |
[2003-9-4 12:01:54] |
| [问：kite] |
我想用AD9851实现一个1Hz~60MHz的信号源，请问DDS后的LPF如何设计？只用一个LPF可以吗？ |
| [答：LWS] |
This is decided by your system requirement. I think one LPF is not
necessary. |
[2003-9-4 12:02:55] |
| [问：samire] |
请介绍DDS的控制接口类型. |
| [答：LWS] |
There are two types: parallel and serial. For the reference codes,
please send mail to china.support@analog.com for technical
support. |
[2003-9-4 12:03:39] |
| [问：72810] |
请教章新明工程师：我在使用AD8345做正交调制时没有使用器件推荐使用的AD转换器件，而是直接使用FPJA产生的数字信号，其电平转换和滤波器设计该怎么实现？我模仿了AD8346的Figure23图的应用，但不知其Cfilter的值的选择依据？ 谢谢 |
| [答：Eagle] |
图23用AD9761＋AD8346，这里可以用AD8345，因为只是频率不同。虽然您用FPGA，一样要用2个DAC，双DAC幅度相位匹配性好。用FPGA做内插占用太多资源，建议使用带内插的TXDAC。FPGA内要把信号变成正交。用0，1，0，-1
和 1，0，-1，0乘最简单。 |
[2003-9-4 12:03:46] |
| [问：ljp] |
重建滤波器的增益误差对输出有何影响?阻带衰耗多大为合适?它和DAC的分辨率有何关系? |
| [答：Pascal] |
The reconstruction gain error - do you mean ripple or insertion
loss?The reconstruction filter will have an attenuation characteristic
which is somewhat sensitive to termination factors.The attenuation
of the stop band is determined by the system requirements. It will also
influence how near to Nyquist that you can push the frequency before the
first image becomes noticable. |
[2003-9-4 12:04:09] |
| [问：39903] |
AD9858的扫频速度最快是多少？谢谢 |
| [答：Pascal] |
125 million frequency steps per second (when sysclock is
1GHz). |
[2003-9-4 12:05:07] |
| [问：kite] |
我想用AD9851设计一个1Hz~60MHz的信号源，请问DSS后的LPF如何设计？只用一个60MHz的椭圆滤波器行吗？Thanks! |
| [答：LWS] |
You have to use more than one filter. |
[2003-9-4 12:05:29] |
| [问：wenedi] |
对于16位的15mhz的输出频率信号，我可不可采用乘法器的方式进行调幅呢 |
| [答：Mariah] |
AD834 and AD835 are multipliers from ADI. They can handle 15MHz
frequency. But the resolution may be too high for them. |
[2003-9-4 12:06:48] |
| [问：11570] |
ad9858的捷变时间极限是多少？与系统时钟的关系如何？ |
| [答：Pascal] |
The minimum time to hop depends on the size of the hop and the PLL
characteristics, if the PLL is in the direct signal path. The hopping
rate, or the rate at which separate frequencies can be output, is limited
by the DDS clock rate. The frequency hopping rate is different for
different DDS models. |
[2003-9-4 12:08:15] |
| [问：49426] |
ad9852的输出为小信号，在输出电路的设计需要注意那些问题 |
| [答：LWS] |
Refer to the datasheet of AD9852. There is the layout and
schematic. |
[2003-9-4 12:08:19] |
| [问：hard22] |
请问用9852如何实现多路数字移相的设计,如何能够保证各路之间的相位的一致和稳定!谢谢! |
| [答：Mariah] |
AD9852 can only do one channel phase shift. you must use two pieces
AD9852. ADI has an application note AN-605 to introduce the
synchronization of multiple AD9852s. |
[2003-9-4 12:08:43] |
| [问：hard22] |
请问:AD9852的参考时钟直接外加的和经过内部PLL倍频,那一种情况输出的信号的频谱好? |
| [答：LWS] |
The external clock will be better. |
[2003-9-4 12:08:48] |
| [问：qin] |
请介绍DDS中的高速数字DDS核的功能和结构. |
| [答：Wayne] |
The heart of the DDS is the Phase Accumulator, which utilizes a
digital Frequency Tuning Word to create a digital phase representation of
the desired frequency. The Phase Accumulator is clocked by the Reference
Clock, or DDS clock.The phase data is then converted to a digital
amplitude in the DDS core by the phase-to-amplitude conversion block. This
produces a digital sine wave signal, which is applied to the DAC –
digital-to-analog converter. The output of the DAC is a time-sampled, or
discrete time, analog signal. The sampling rate is, again, determined by
the Reference, or DDS, clock which is the heartbeat of the DDS.Because
the output from the DDS is a time-sampled analog signal, it contains both
the intended analog sine wave (of the desired frequency) and a typical
spectrum of images. These images must be filtered out by a low-pass
filter, also known as a reconstruction filter. This filter typically is
external to the DDS IC. The signal available at the output of the
reconstruction filter is a very clean analog sine wave of very precise and
stable frequency. |
[2003-9-4 12:09:08] |
| [问：ljp] |
DAC的取样频率和低通滤波器的带宽关系. |
| [答：Eagle] |
根据采样定律，滤波器截止频率必须小于DAC时钟的1/2，由于有过渡带，实际低通滤波器带宽只有39％时钟频率以下。这也是为什么AD985x
和AD995x系列DDS只用到DDS时钟的39％以下。 |
[2003-9-4 12:09:09] |
| [问：95153] |
9858布板时需要注意的问题都有哪些？特别是对它的高速时钟有什么特别处理？ |
| [答：Pascal] |
The clock signal should be differential. It should be routed over
short path of impedence controlled transmission line. You can use
microstip or stripline techniques on PCB. Try not to run the clock lines
over noisy lines. |
[2003-9-4 12:10:22] |
| [问：40445] |
对ad9852进行编程时是否要对每一个控制寄存器输入数据，在用串行方式下对控制寄存器地址输入数据是否有顺序 |
| [答：LWS] |
Yes. Please refer to the datasheet for the timing. Or send mail to
china.support@analog.com for the example code. Call 800 810 1742 for
technical support. |
[2003-9-4 12:10:38] |
| [问：71809] |
DDS的评估板大多是四层板，请问双层板对性能有何影响。谢谢！ |
| [答：Eagle] |
布线好也可用，这是要将底层变为几乎全为地。注意同样线宽，层数不同时，特性阻抗会变。 |
[2003-9-4 12:10:53] |
| [问：ljp] |
现在你介绍的是DDS+PLL,有无可能是PLL+DDS组合?即用PLL驱动DDS. |
| [答：Eagle] |
DDS的时钟有很多时候是用PLL产生的。 |
[2003-9-4 12:11:34] |
| [问：49426] |
请问AD9852输出线性调频信号的输出滤波器的设计有什么要求 |
| [答：LWS] |
You have to specify the filter"s bandwidth, out of band rejection, in
band ripple. |
[2003-9-4 12:11:52] |
| [问：DeFatta] |
DDS芯片的AGND,DGND是分开接地，还是接在一起？ |
| [答：LWS] |
Please connect them together for high speed converters and
DDS. |
[2003-9-4 12:13:06] |
| [问：qin] |
DDS参考时钟源对DDS的输出有何影响?频率关系如何计算?决定的因素是什么? |
| [答：Mariah] |
The quality of the reference clock will greatly influence the DDS
output. You can find the frequency calculation formula from the datasheet.
You can find the DDS basics to get more information from the link
below:http://www.analog.com/UploadedFiles/Tutorials/
54011189110016515183343533079104002517DDStutor.pdf |
[2003-9-4 12:13:11] |
| [问：84753] |
我想得到一款不含正弦ROM和D/A合成器的DDS,ADI是否有这样的产品 |
| [答：LWS] |
Is this DDS? |
[2003-9-4 12:14:14] |
| [问：ecnan
jing_EB
Y7E] |
用DDS作为虚拟仪器的扫频源,扫频范围是10KHz-10MHz,请问采用什型号的DDS为好？ |
| [答：Eagle] |
一般用AD9850就可以了。如果您要特便宜，也可考虑AD9831、AD9833。 |
[2003-9-4 12:15:06] |
| [问：samire] |
DDS中的DAC输出是单端或差分输出?驱动能力有多大? |
| [答：LWS] |
It is current output. when you want to drive other devices, please use
an amplifier after it. |
[2003-9-4 12:16:51] |
| [问：18738] |
请问，用dds ad9850 和pll
组成的频合器能支持多高的跳频速度？ |
| [答：LWS] |
It is decided by the AD9850"s interface speed. |
[2003-9-4 12:17:54] |
| [问：90721] |
我想知道在演讲第26张幻灯片上，对系统时钟源有什么要求？谢。 |
| [答：Pascal] |
The system clock should be as clean as possible, because the DDS will
reflect any defects in its system clock. The frequency of the system clock
depends both on the system frequency plan, and the ability of the DDS.
Usually, a DDS should be clocked at or near its maximum spec"d
rate. |
[2003-9-4 12:18:02] |
| [问：liu
chunyang] |
AD9854和AD9852的评估板除芯片和软件不一样，其它部分是一样吗？ |
| [答：LWS] |
The software is the same. AD9852 has two outputs, AD9854"s two output
is quadrature. |
[2003-9-4 12:18:51] |
| [问：ljp] |
如何降低DDS的功耗?目前的水平是多少? |
| [答：Eagle] |
请注意时钟速度和字长对功耗影响很大。AD9954就是低功耗的,它用1.8V Power
Supply。当然AD9833也是低功耗。AD9833 is 20 mW Power Consumption at 3 V。 |
[2003-9-4 12:18:52] |
| [问：hard22] |
如何用DDS实现数字移相的设计?谢谢! |
| [答：Pascal] |
Most of ADI DDS feature a phase offset capability. Some of the DDS +
PLL architectures, though, nullify the phase control ability because of
the PLL loop. However, the designs where the PLL is not in the direct
signal path can make use of the phase control capabilities of the
DDS. |
[2003-9-4 12:19:49] |
| [问：liu
chunyang] |
DAC的位数主要是影响DDS输出信号的哪些参数？ |
| [答：Eagle] |
对SNR和SFDR影响很大。当然，要看瓶颈在哪头。 |
[2003-9-4 12:19:57] |
| [问：89279] |
如果用AD9858实现宽带线性调频信号，可不可以利AD9858产生的线性调频信号作为基准去驱动内部的PLL而得到射频信号？ |
| [答：Wayne] |
Yes, you can refer to the fig 36 on the datasheet of AD9858. It"s just
a example of this kind of application. |
[2003-9-4 12:20:39] |
| [问：YCZCF] |
AD9852在工作时温度达到80度以上，设计PCB时，应注意哪些方面？ |
| [答：LWS] |
You have to calculate the power dissipation. And please select the
right package. When do layout, try to use the PCB"s ground to distribute
the heat. refer to the EVB of AD9852 is a good practice. |
[2003-9-4 12:21:48] |
| [问：tang
weiliang] |
DDS中一般采用CIC作为插入滤波器，该种滤波器有什么优势？ |
| [答：LWS] |
It is easy to design. Refer
tohttp://www.analog.com/UploadedFiles/Tutorials/
54011189110016515183343533079104002517DDStutor.pdfPlease. |
[2003-9-4 12:22:36] |
| [问：tang
weiliang] |
在我们使用AD9857过程中，经过椭圆滤波器后出现自激现象，这是由什么原因引起的。 |
| [答：LWS] |
This is because the design of your filter. So simulate your filter
before you use it. |
[2003-9-4 12:23:38] |
| [问：95153] |
脉冲调幅中，脉冲的休止期的零输出怎么实现?能不能通过将频率置零的方法，或者shut
down的方式？谢谢 |
| [答：Pascal] |
On the AD9852, AD9854, AD995X DDSs there is a pin for OSK - output
shift keying. This can be used to control the output on or off, either
abruptly or in a ramped fashion. Also, programming zero output frequency
accomplishes a zero RF output. There remains a DC offset,
however.Normally I wouldn"t recommend the power down mode for this
use. |
[2003-9-4 12:24:07] |
| [问：tang
weiliang] |
如何解决载波抑制问题？ |
| [答：LWS] |
The carrier"s rejection is decided by the part itself. If the carrier
is far from the signal you wanted, you can use filter to reject
it. |
[2003-9-4 12:24:57] |
| [问：39903] |
请问DDS的输出经过多次倍频后杂散会变坏么？谢谢 |
| [答：Wayne] |
Normally PLL can reduce the spurs inherent in a DDS spectrum, creating
a cleaner RF output. Meanwhile a DDS allows for a lower frequency gain in
a PLL loop, thereby enhancing the phase noise performance of a
synthesizer. |
[2003-9-4 12:25:34] |
| [问：65577] |
从我的理解，DDS对于相噪的改善主要在于取决于参考时钟源，而不象PLL取决于VCO，对吗？另外，既然现实的DDS输出频率不超过400M,能推荐一两家工作在800M以上的参考源吗？ |
| [答：Eagle] |
如果相位累加器字长够长，幅度查找表字长和DAC位数也很长，那么时钟频率就取决定作用了。可参考DDS_Tutorial_rev12-2-99.pdf。请联系技术支持中心：China
Application Support Team Toll-free Call Number: 800 810 1742 FAX Number:
800 810 1747ADI analog products China Support Center Email:
China.support@analog.com |
[2003-9-4 12:25:36] |
| [问：55033] |
产生I、Q两路信号的DDS芯片，可否调节其相位 |
| [答：LWS] |
AD9854 has the phase shifting capability. |
[2003-9-4 12:26:00] |
| [问：19423] |
请问使用AD9858输出信号的杂散能抑制到何种程度？其后使用倍频器对杂散影响大吗？相位噪声呢？ |
| [答：Mariah] |
The SFDR is depending on the clock reference ,the output frequency and
the layout ,etc. You can get the figure in the datasheet under different
conditions. The multiplier will influence the SFDR. |
[2003-9-4 12:27:28] |
| [问：19410] |
AD9858输出信号的质量主要与什么有关 |
| [答：LWS] |
This is decided by the configuration. And normally the clock quality
and the filter quality is important. |
[2003-9-4 12:28:08] |
| [问：tang
weiliang] |
我们在使用AD9857时，发现它的输出信号的波形并不是很好，其信噪比不高，带外衰减性能不是很好，不知造成该问题的原因是什么呢？ |
| [答：Eagle] |
1.请检查您的低通滤波器特性。2.请检查时钟。可以用10M标准频率直接输入，注意匹配。3.注意布线。4.请参考评估板。 |
[2003-9-4 12:28:19] |
| [问：19410] |
AGND DGND在什么地方连在一起，芯片附近还是其他地方？ |
| [答：LWS] |
Connect them together at the system ground. Normally you can connect
them at the power input point. But refer to the EVB will be a good
pratice. |
[2003-9-4 12:29:19] |
| [问：cagwcagw] |
Mr. Wayne:
按照您的解释，ADI的DDS并不能直接用于任意波形合成，是这样吗？/ According to your explanation, ADI DDS
can not be used in arbitray signal generator directly. Does it?
Thanks. |
| [答：Wayne] |
Yes, present DDS can"t generate arbitrary signal. We"ve plan to do
that function in the near future. |
[2003-9-4 12:29:30] |
| [问：jjsen] |
DDS的实际输出频率精度有多高？ |
| [答：Pascal] |
The DDS output accuracy is determined by the accuracy of the refernce
clock. The tuning resolution is determined by the width of the frequency
accumulator - either 32 bits or 48 bits. For example, an AD9852 with 48
bit tuning word and 300MHz refclock has a tuning resolution of the order
of 1 micro Hz. However, the accuracy is the same as the refernce
clock. |
[2003-9-4 12:29:52] |
| [问：77850] |
在线性调频或跳频方式下的相位噪声和杂散指标是否较工作在单个点频模式下的差 |
| [答：Pascal] |
No. The hopping doesn"t change the inherent phase noise and SFDR, but
since hopping is a change in frequency, the SFDR may be different at
different frequencies, as you hop through them. |
[2003-9-4 12:30:55] |
| [问：qiangnet] |
hi,can you tell me how power supply noise
degrades the output jitter performance of pll.thanks a
lot! |
| [答：Pascal] |
The power supply noise can be very destructive if it can get onto the
charge pump integrator or loop filter. You should take great efforts to
keep the power supply as clean as possible, especially at the PLL
(bypassing is important). The loop filter should be especially protected
from induced noise. |
[2003-9-4 12:32:39] |
| [问：alongsh] |
ad9858输出的线性调频信号要搬移到GHZ，可不可以用该信号作为AD9858片内PLL鉴相器的输入信号来闭环实现？ |
| [答：Wayne] |
GHz signal can"t be input directly, but you can do that after deviding
it to a range under 150MHz. |
[2003-9-4 12:33:19] |
| [问：alongsh] |
要用DDS和PLL实现一个带宽为200m的S波段的线性扫频源，用ADI的什么产品比较好？ |
| [答：Eagle] |
只有AD9858较好，也可用AD9954＋ADF4107，但要分段考虑。AD9858 (32 Bit DDS, D/A=10
Bit, Iout=4>40mA, Ext Fclock=2GHz, Int Clock=Ext Clock/2, Wideband
/Narrow SFRD=52/84dBc @ 360MHz, Phase Noise=-130dBc @ 1KHz Offset,
Vsys=+3.3 @ 575mA, I/O=8 Bit, w/on Chip Mixer & Phase Frequency
Detector) |
[2003-9-4 12:34:22] |
| [问：19410] |
AD9858可不可以实现四相码调制 |
| [答：LWS] |
No, it cannot. |
[2003-9-4 12:35:42] |
| [问：liu
chunyang] |
我用过AD9854,感觉Invers SINC
滤波器对高频信号的幅度没有多大的改善,在应用时要注意什么吗? |
| [答：Pascal] |
The inverse SINC filter is a leveling or flattening filter. It works
across the entire Nyquist region. I"m not sure what else is in your
question. |
[2003-9-4 12:35:54] |
| [问：89279] |
如果用AD9858实现带宽为150MHZ(1925-2075MHZ）的线性调频信号，可以用刚才提到的频移环路（AD9858+lpf+宽带VCO）吗？ |
| [答：Mariah] |
Yes, you can do it by DDS+PLL scheme as the presentation
shows. |
[2003-9-4 12:36:50] |
| [问：DeFatta] |
能否用DDS的SHAPE ON功能来实现AM调制？ |
| [答：Pascal] |
Yes. You can use the output scaler to do AM, as long as the required
bandwidth is less than the update capability of the DDS. That is, how fast
can you write new values to the output scaler and update. |
[2003-9-4 12:38:23] |
| [问：cagwcagw] |
在短波软件无线电中，能否用DDS直接实现中频调制波形合成，包括AM,DSB,SSB,FM等？建议使用什么样的芯片，推荐的中频频率是多少，要配合什么样的DSP? |
| [答：Wayne] |
Yes, you can generate IF modulating signal directly with DDS. As your
RF is about 30MHz frenquency, so the modulating signal should be lower
frequency, therefore AD983x can be enough. You can use Sharc series
ADSP2116x/06x, and Blackfin series BF53x (fixed point with MCU function
integrated). |
[2003-9-4 12:39:25] |
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